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dear customers, about the change in the name such as "oki electric industry co. ltd." and "oki" in documents to oki semiconductor co., ltd. the semiconductor business of oki electric industry co., ltd. was succeeded to oki semiconductor co., ltd. on oc tober 1, 2008. therefore, please accept that although the terms and marks of "oki electric indust ry co., ltd.", ?oki electric?, and "oki" remain in the documents, they all have been changed to "oki semiconductor co., ltd.". it is a change of the company name, the co mpany trademark, and the logo, etc. , and not a content change in documents. october 1, 2008 oki semiconductor co., ltd. 550-1 higashiasakawa-cho, hachio ji-shi, tokyo 193-8550, japan http://www.okisemi.com/en/
1/17 ? semiconductor msm514256c/cl description the msm514256c/cl is a 262,144-word 4-bit dynamic ram fabricated in oki's silicon-gate cmos technology. the msm514256c/cl achieves high integration, high-speed operation, and low-power consumption because oki manufactures the device in a quadruple-layer polysilicon/single-layer metal cmos process. the msm514256c/cl is available in a 20-pin plastic dip, 26/20-pin plastic soj, or 20-pin plastic zip. the msm514256cl (the low-power version) is specially designed for lower-power applications. features ? 262,144-word 4-bit configuration ? single 5 v power supply, 10% tolerance ? input : ttl compatible, low input capacitance ? output : ttl compatible, 3-state ? refresh : 512 cycles/8 ms, 512 cycles/64 ms (l-version) ? fast page mode, read modify write capability ? cas before ras refresh, hidden refresh, ras -only refresh capability ? package options: 20-pin 300 mil plastic dip (dip20-p-300-2.54-w1) (product : msm514256c/cl-xxrs) 26/20-pin 300 mil plastic soj (soj26/20-p-300-1.27) (product : msm514256c/cl-xxjs) 20-pin 400 mil plastic zip (zip20-p-400-1.27) (product : msm514256c/cl-xxzs) xx indicates speed rank. product family ? semiconductor msm514256c/cl 262,144-word 4-bit dynamic ram : fast page mode type msm514256c/cl-50 50 ns 100 ns 120 ns 446 mw 385 mw 5.5 mw/ family access time (max.) cycle time (min.) standby (max.) power dissipation msm514256c/cl-60 t rac 60 ns 26 ns t aa 30 ns 14 ns t cac 15 ns msm514256c/cl-45 45 ns 90 ns 468 mw 24 ns 14 ns operating (max.) 1.1 mw (l-version) 130 ns 330 mw msm514256c/cl-70 70 ns 35 ns 20 ns 14 ns t oea 15 ns 14 ns 20 ns e2g0010-17-41 this version: jan. 1998 previous version: may 1997
2/17 ? semiconductor msm514256c/cl pin configuration (top view) 20-pin plastic dip 26/20-pin plastic soj 20-pin plastic zip pin name function a0 - a8 address input ras row address strobe cas column address strobe dq1 - dq4 data input/data output oe output enable we write enable v cc power supply (5 v) v ss ground (0 v) 3 5 7 11 13 15 17 19 dq3 v ss dq2 a0 a2 v cc a5 a7 1 oe 9 ras 4 6 8 12 14 16 18 20 dq4 dq1 we a1 a3 a4 a6 a8 2 cas no lead 3 4 5 9 10 11 12 13 we ras nc a0 a1 a2 a3 v cc 24 23 22 18 17 16 15 14 dq3 cas oe a8 a7 a6 a5 a4 2 dq2 25 dq4 1 dq1 26 v ss 1 dq1 10 v cc 2 dq2 3 we 4 ras 5 nc 6 a0 7 a1 8 a2 9 a3 20 v ss 11 a4 19 dq4 18 dq3 17 cas 16 oe 15 a8 14 a7 13 a6 12 a5 nc no connection
3/17 ? semiconductor msm514256c/cl block diagram timing generator ras cas timing generator internal address counter row address buffers a0 - a8 v cc v ss on chip v bb generator row de- coders word drivers memory cells refresh control clock sense amplifiers column decoders write clock generator i/o selector output buffers we oe 4 dq1 - dq4 4 4 4 4 4 input buffers 4 9 99 column address buffers 9
4/17 ? semiconductor msm514256c/cl electrical characteristics absolute maximum ratings recommended operating conditions capacitance *: ta = 25 c voltage on any pin relative to v ss short circuit output current power dissipation operating temperature storage temperature v t symbol i os p d * t opr t stg C1.0 to 7.0 50 1 0 to 70 C55 to 150 rating ma w c c parameter v unit power supply voltage input high voltage input low voltage v cc symbol v ss v ih v il 5.0 0 typ. parameter 4.5 0 2.4 C1.0 min. 5.5 0 6.5 0.8 max. (ta = 0c to 70c) v unit v v v input capacitance (a0 - a8) input capacitance ( ras , cas , we , oe ) output capacitance (dq1 - dq4) c in1 symbol c in2 c i/o 5 5 6 max. pf unit pf pf parameter (v cc = 5 v 10%, ta = 25c, f = 1 mhz) typ.
5/17 ? semiconductor msm514256c/cl dc characteristics i oh = C5.0 ma output high voltage i ol = 4.2 ma output low voltage 0 v v i 6.5 v; all other pins not input leakage current under test = 0 v dq disable output leakage current 0 v v o 5.5 v ras , cas cycling, average power t rc = min. supply current (operating) ras , cas = v ih power supply ras , cas current (standby) ras cycling, average power cas = v ih , supply current t rc = min. ( ras -only refresh) ras = v ih , power supply cas = v il , current (standby) dq = enable average power cas before ras supply current ( cas before ras refresh) ras = v il , average power cas cycling, supply current t pc = min. (fast page mode) t rc = 125 m s, average power cas before ras , supply current t ras 1 m s (battery backup) 3 v cc C0.2 v v v m a m a ma ma ma ma ma ma m a m a ras cycling, parameter symbol condition v oh v ol i li i lo i cc1 i cc2 i cc3 i cc5 i cc6 i cc7 i cc10 msm514256 c/cl-45 msm514256 c/cl-50 msm514256 c/cl-60 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 85 1 200 85 5 85 80 300 2 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 80 1 200 80 5 80 75 300 2 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 70 1 200 70 5 70 65 300 2 unit (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2 1, 5 1, 2 1 1, 2 1, 3 1, 2, 4, 5 1 msm514256 c/cl-70 min. 2.4 0 C10 C10 max. v cc 0.4 10 10 60 1 200 60 5 60 55 300 2 notes : 1. i cc max. is specified as i cc for output open condition. 2. the address can be changed once or less while ras = v il . 3. the address can be changed once or less while cas = v ih . 4. v cc C 0.2 v v ih 6.5 v, C1.0 v v il 0.2 v. 5. l-version.
6/17 ? semiconductor msm514256c/cl ac characteristics (1/2) random read or write cycle time read modify write cycle time fast page mode cycle time fast page mode read modify write cycle time access time from ras access time from cas access time from column address access time from oe output low impedance time from cas transition time refresh period refresh period (l-version) ras precharge time ras pulse width (fast page mode) ras hold time cas precharge time (fast page mode) cas pulse width ras pulse width cas hold time cas to ras precharge time ras to cas delay time ras to column address delay time row address set-up time row address hold time column address set-up time column address hold time column address hold time from ras column address to ras lead time access time from cas precharge oe to data output buffer turn-off delay time ras hold time referenced to oe ras hold time from cas precharge cas to data output buffer turn-off delay time t rc t rwc t pc t prwc t rac t cac t aa t oea t clz t off t t t ref t ref t rp t ras t rasp t rsh t cp t cas t csh t crp t rcd t rad t asr t rah t asc t cah t ar t ral t cpa t oez t roh t rhcp parameter msm514256 c/cl-45 msm514256 c/cl-50 msm514256 c/cl-60 msm514256 c/cl-70 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 4, 5 symbol min. 90 140 34 75 0 0 3 35 45 45 14 10 14 45 5 17 12 0 7 0 12 35 24 0 10 max. 45 14 24 28 10 50 8 64 10,000 100,000 10,000 31 21 14 10 min. 100 150 36 77 0 0 3 40 50 50 14 10 14 50 5 18 13 0 8 0 13 40 26 0 10 max. 50 14 26 30 10 50 8 64 10,000 100,000 10,000 36 24 14 10 min. 120 170 40 90 0 0 3 50 60 60 15 10 15 60 5 20 15 0 10 0 15 50 30 0 10 max. 60 15 30 35 10 50 8 64 10,000 100,000 10,000 45 30 15 10 min. 130 185 45 95 0 0 3 50 70 70 20 10 20 70 5 20 15 0 10 0 15 55 35 0 10 max. 70 20 35 40 10 50 8 64 10,000 100,000 10,000 50 35 20 10 unit ns ns ns ns ns ns ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns note 6, 7, 8 6, 7 6, 8 6 6 9 3 7 8 6 9 28303540ns
7/17 ? semiconductor msm514256c/cl ac characteristics (2/2) read command set-up time t rcs read command hold time t rch read command hold time referenced to ras write command set-up time write command hold time write command hold time from ras write command pulse width write command to ras lead time write command to cas lead time data-in set-up time t rrh t wcs t wch t wcr t wp t rwl t cwl t ds data-in hold time t dh data-in hold time from ras t dhr cas to we delay time t cwd column address to we delay time t awd ras to we delay time cas active delay time from ras precharge ras to cas set-up time ( cas before ras ) ras to cas hold time ( cas before ras ) t rwd t rpc t csr t chr oe command hold time t oeh oe to data-in delay time t oed cas precharge we delay time t cpwd parameter msm514256 c/cl-45 msm514256 c/cl-50 msm514256 c/cl-60 msm514256 c/cl-70 (v cc = 5 v 10%, ta = 0c to 70c) note 1, 2, 3, 4, 5 symbol min. 0 0 0 0 10 12 35 14 0 12 35 12 48 70 50 0 10 25 36 10 max. unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. 0 0 0 0 10 13 40 14 0 13 40 13 52 75 53 0 10 25 38 10 max. min. 0 0 0 0 10 15 50 15 0 15 50 15 60 90 60 0 10 30 50 10 max. min. 0 0 0 0 15 20 55 20 0 15 55 20 65 100 70 0 10 30 50 15 max. note 10 10 11 12 12 11 11 11 11 14 ns 14 15 20
8/17 ? semiconductor msm514256c/cl notes: 1. a start-up delay of 100 m s is required after power-up, followed by a minimum of eight initialization cycles ( ras -only refresh or cas before ras refresh) before proper device operation is achieved. 2. the ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring input timing signals. transition times (t t ) are measured between v ih and v il . 4. v ih = 3.0 v and v il = 0.0 v are reference levels for measuring input timing signals (speed ranks 45 and 50). 5. v ih = 2.4 v and v il = 0.8 v are reference levels for measuring input timing signals (speed ranks 60 and 70). 6. this parameter is measured with a load circuit equivalent to 2 ttl loads and 100 pf. 7. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then the access time is controlled by t cac . 8. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then the access time is controlled by t aa . 9. t off (max.) and t oez (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 10. t rch or t rrh must be satisfied for a read cycle. 11. t wcs , t cwd , t rwd , t awd and t cpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. if t cwd 3 t cwd (min.) , t rwd 3 t rwd (min.), t awd 3 t awd (min.) and t cpwd 3 t cpwd (min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 12. these parameters are referenced to the cas leading edge in an early write cycle, and to the we leading edge in an oe control write cycle, or a read modify write cycle.
9/17 ? semiconductor msm514256c/cl timing waveform read cycle "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t rcd t csh t rsh t crp t cas t rad t rah t asr t asc t cah row column t wcs t wch t wcr t dhr t ds t dh valid data-in t wp t ral open t cwl t rwl "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rc t ras t rp t ar t crp t csh t crp t rcd t rsh t cas t rad t asr t rah t asc t cah t ral row column t rcs t rrh t rch t aa t roh t oea t cac t rac t oez t off open t clz valid data-out write cycle (early write) e2g0092-17-41e
10/17 ? semiconductor msm514256c/cl "h" or "l" ras cas v ih v il C C v ih v il C C dq v i/oh v i/ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rwc t ras t rp t ar t crp t csh t rcd t crp t rsh t cas t asr t rah t asc t cah row column t cwd t cwl t rwd t rwl t wp t aa t awd t oea t oed t cac t rac t oez t ds t dh t clz valid data-out valid data-in t rad t rcs t oeh read modify write cycle
11/17 ? semiconductor msm514256c/cl fast page mode read cycle fast page mode write cycle (early write) "h" or "l" ras cas v ih v il C C v ih v il C C dq v ih v il C C address v il C C we v ih v il C C t rasp t rp t ar t crp t rcd t cas t cp t cas t rsh t crp t cas t asr t rah t cah t csh t asc t cah t asc t cah t ral row column column column t rad t wcs t wch t wp t wcs t wch t wp t wcs t wch t wp t ds t dh t ds t dh t ds t dh valid data-in valid data-in valid data-in t dhr note: oe = "h" or "l" v ih t asc t pc t rhcp t cp t cwl t cwl t rwl t cwl t wcr "h" or "l" ras cas v ih v il C C v ih v il C C dq v oh v ol C C address v ih v il C C we v ih v il C C oe v ih v il C C t rasp t rp t ar t crp t rcd t pc t rsh t crp t cas t cas t cp t cas t rad t asr t rah t asc t cah t csh t asc t cah t asc t cah t ral row column column column t rcs t rch t rcs t rcs t rch t aa t oea t aa t aa t rrh t oea t oea t cac t rac t off t oez t cac t clz t off t oez t cac t clz t oez t off t clz valid data-out valid data-out valid data-out t rhcp t cp t rch t cpa t cpa
12/17 ? semiconductor msm514256c/cl ras cas v ih v il C C v ih v il C C address v ih v il C C t rc t ras t rp t crp t rpc t asr t rah row "h" or "l" dq v oh v ol e e note: we , oe = "h" or "l" open t off fast page mode read modify write cycle t wp ras cas address oe v ih v il C C v ih v il C C v ih v il C C v ih v il C C we v ih v il C C dq v i/oh v i/ol C C t rasp t ar t rp t csh t prwc t rsh t rcd t cas t cp t cas t cp t cas t crp t rad t rah t asr t asc t cah t asc t cah t asc t cah t ral row column column column t rwd t rcs t cwd t cwl t cwd t cwl t cwd t rwl t cwl t awd t awd t awd t oea t wp t oea t wp t oea t aa t oed t cac t ds t dh t cac t aa t rac t ds t dh t cpa t oed t cac t aa t ds t dh t clz t clz t clz out in out out in in t roh t oez t oez t cpa t oed t rcs t rcs t cpwd t cpwd "h" or "l" t oez ras -only refresh cycle
13/17 ? semiconductor msm514256c/cl ras cas v ih v il C C v ih v il C C column row dq v oh v ol C C we v ih v il C C oe v ih v il C C address v ih v il C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asr t asc t rah t cah t rcs t ral t rrh t aa t roh t oea t cac t clz t rac t off t oez valid data-out "h" or "l" cas before ras refresh cycle hidden refresh read cycle ras cas v ih v il C C v ih v il C C t chr note: we , oe , address = "h" or "l" dq v oh v ol C C t rc t rp t ras t rp t rpc t cp t csr t rpc t off open "h" or "l"
14/17 ? semiconductor msm514256c/cl hidden refresh write cycle ras cas v ih v il C C v ih v il C C dq v ih v il C C we v ih v il C C oe v ih v il C C address v ih v il C C t rc t rc t ras t rp t ras t rp t ar t crp t rcd t rsh t chr t rad t asc t asr t rah t cah t ral row column t wcs t wch t wp t ds t dh valid data-in t dhr "h" or "l" t wcr
15/17 ? semiconductor msm514256c/cl (unit : mm) package dimensions dip20-p-300-2.54-w1 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.50 typ.
16/17 ? semiconductor msm514256c/cl (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). soj26/20-p-300-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.80 typ. mirror finish
17/17 ? semiconductor msm514256c/cl (unit : mm) zip20-p-400-1.27 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 1.50 typ. mirror finish

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